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[VHDL-FPGA-Verilog] SPI

Description: 利用VHDL实现spi，IPcode 的 spi-Using VHDL implementation spi, IPcode the spi
Platform: | Size: 51200 | Author: liwei | Hits:

[VHDL-FPGA-Verilog] ad_test

Description: ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现-ad9777 test procedures, the SPI is initialized, the use of ISE environment, the successful realization of comprehensive and
Platform: | Size: 2665472 | Author: 关明明 | Hits:

[VHDL-FPGA-Verilog] Verilog000

Description: FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。
Platform: | Size: 22794240 | Author: onejacky | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
Platform: | Size: 13312 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] FPGA_SPI.ZIP

Description: 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
Platform: | Size: 1024 | Author: shoucql | Hits:

[VHDL-FPGA-Verilog] VHD_Veri_spi

Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
Platform: | Size: 13312 | Author: 中国 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: SPI总线通信模块，经测试验证通过的源码-SPI vhdl source code
Platform: | Size: 329728 | Author: victor | Hits:

[VHDL-FPGA-Verilog] Exp6_SPI_AD_DA

Description: 用VHDL在SOPC试验箱中实现DA_AD转换，用ＶＨＤＬ硬件描述语言实现处理器CPU-With VHDL SOPC test box in DA_AD realization, with VHDL language processor CPU hardware description
Platform: | Size: 12840960 | Author: jiajinying | Hits:

[VHDL-FPGA-Verilog] AD9512_VHDL

Description: FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序，在需要用到高速时钟（GHz）的电路中经常采用，比如数据采集卡及信号回放卡中会经常用到该功能，已经在产品中得到验证，工作稳定。-The VHDL code of controlling AD9512 of Analog Device
Platform: | Size: 3072 | Author: 傅其祥 | Hits:

[VHDL-FPGA-Verilog] Flash_Ctrl

Description: 串行flash的写及擦除操作，串行flash，spi接口，支持并口输出-Serial flash write and erase operations, serial flash, spi interface, support for parallel port output
Platform: | Size: 1024 | Author: 王伯祥 | Hits:

[VHDL-FPGA-Verilog] SD_SPI

Description: sd卡spi接口的verilog程序，quartus2,全部调好能已经应用于SD卡模块。-sd card spi interface verilog program, quartus2, all tuned to have been used in SD card module.
Platform: | Size: 2700288 | Author: 洪传荣 | Hits:

[VHDL-FPGA-Verilog] VHDL-based-design-of-SPI

Description: 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design process. According to both send and receive SPI implements the main part of the basic functions. In addition, the design also implements the baud rate generator, digital display features. DE2 board to achieve a circuit with a simple, short development cycle advantages. Full use of the EDA design advantages. Development Process VHDL hardware description language used to describe the design from the ground, sub-module, to fully enhance the designer' s concept of digital logic design.
Platform: | Size: 51200 | Author: 陈添 | Hits:

[VHDL-FPGA-Verilog] SPI_interface(VHDL)

Description: SPI接口模块源代码（VHDL）语言，经过产品应用测试。-SPI interface module source code (VHDL language), after product application testing.
Platform: | Size: 1024 | Author: Field | Hits:

[VHDL-FPGA-Verilog] CoreSPI_21_eval

Description: SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages ​ ​ Verilog and VHDL source code
Platform: | Size: 628736 | Author: 任林枫 | Hits:

[VHDL-FPGA-Verilog] spi_int

Description: realize spi interface vhdl code xilinx help ths help developers
Platform: | Size: 65536 | Author: Antoshka | Hits:

[VHDL-FPGA-Verilog] spi

Description: 描述了总线的vhdl程序，并且有测试语句的描写 仿真之后可以实现-Describes the bus vhdl program, and a test statement, after describing the simulation can be achieved
Platform: | Size: 1024 | Author: 王韩 | Hits:

[VHDL-FPGA-Verilog] Altera-memory

Description: 这个软件是altera 芯片对SPIflash的一个控制程序，里面读写测试已经通过。-spi flash code for VHDL
Platform: | Size: 125952 | Author: 周明 | Hits:

[VHDL-FPGA-Verilog] spi_vhdl

Description: vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
Platform: | Size: 6144 | Author: 站长 | Hits:

[VHDL-FPGA-Verilog] spi

Description: 一个vhdl开发的spi总线的控制程序，很有广泛性，可做参考-spi based on vhdl
Platform: | Size: 2048 | Author: coolxgz | Hits:

[VHDL-FPGA-Verilog] FPGA_SPI_VHDL

Description: 串行外设接口（SPI）fpga 被动接收,在下降沿 采集数据并发送数据 1BYTE,要求mcu在末端采集数据。并在下降沿之前准备好数据。-Serial Peripheral Interface (SPI), The fpga passive receiving, at the falling edge of data collection the send data 1BYTE, mcu data collected at the end. And the data ready before the falling edge.
Platform: | Size: 8192 | Author: fxh | Hits:
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